This section describes how and where clock signals are routed. Switches symbolize connections that can be altered by placement of capacitors. Default connection is symbolized by switch position.
OSC1 - 50 MHz main clock source for FPGA resources
OSC2 - 200 MHz clock for MGT
Metlino cards recover their DRTIO clock from their SFP/SATA transciever link. DRTIO documentation is here.